1. Field of the Invention
The present invention relates to logic device control.
2. Discussion of the Related Art
In many electronic systems, a master device sends commands to slave devices to request data stored in the slave devices. In such a system, a master device sends an identification word (xe2x80x9cIDxe2x80x9d) along with the command to a slave device. In response, the slave device returns the ID along with a response, so as to allow the master device to match the response with the corresponding command.
Often, to acknowledge receipt of a command, a slave device sends an acknowledgment signal, which is timed to indicate the slave device""s response time in clock cycles. For example, an acknowledgment signal from a slave device is xe2x80x9cone earlyxe2x80x9d if the slave device sends the acknowledgment signal one clock cycle prior to sending the response to a command. The response time indicated by the acknowledgment signal is referred to as the xe2x80x9ctiming semanticsxe2x80x9d of the acknowledgment signal. Thus, by using the timing semantics of an acknowledgment signal and returning the ID in the acknowledgment signal, the slave device acknowledges receipt of the command and indicates a response time.
In certain applications, a control sequence circuit uses a slave device""s response to a master device""s command to synchronize control signals to different logic devices. For example, an application may require four logic devices to receive control signals successively over four clock cycles, beginning at the clock cycle immediately prior to a slave device""s response to a master device""s command. However, as designs change, the timing semantics of the acknowledgment signal may change while the synchronization of the sequence of commands to the response by the slave device remains the same. Thus, there is also a need for a control sequencer circuit that can be adjusted to the timing semantics of the acknowledgment signal of the slave device.
The present invention provides a control sequencer circuit that issues a sequence of commands synchronized to a slave device""s response to a command. The control sequencer uses the acknowledgment signal from the slave device to time the command sequence with the slave device""s response. Furthermore, the control sequencer circuit is statically adjusted to the timing semantics of the acknowledgment signal of the slave device.
The control sequencer circuit includes an event detector, a static sliding window, and a control sequencer stage. The event detector is a circuit coupled to receive an acknowledgment signal and a requester ID from the slave device. When the event detector receives (1) an active acknowledgment signal and (2) a requester ID that matches an ID hardwired to the event detector, it sends an active signal A to the static sliding window. After sending an active signal A, the event detector cannot send another active signal A until it receives an active signal INTERLOCK from the control sequencer stage indicating that a sequence of commands has been sent. This feature prevents the control sequencer circuit from generating a subsequent sequence of commands before a prior sequence of commands has been sent.
The static sliding window is a circuit that synchronizes the command sequence (which is generated by the control sequencer stage) to the slave device""s response. When the static sliding window receives an active signal from the event detector, it creates an appropriate delay before sending the active signal to the control sequencer stage. The delay synchronizes the command sequence to the response by the slave device and adjusts for the timing semantics of the acknowledgment signal of the slave device.
In one embodiment, the static sliding window includes a buffer that immediately transmit the active signal to the control sequencer stage. In another embodiment, the static sliding window includes a delay element (e.g., a flip-flop) that creates a one-clock cycle delay before sending the active signal to the control sequencer stage. In yet another embodiment, the static sliding window includes a number of delay elements that create a multi-clock cycle delay before sending the active signal to the control sequencer stage.
The control sequencer stage includes a chain of delay elements. After receiving the active signal from the static sliding window, each delay element successively outputs an active signal at each clock cycle, thereby generating the command sequence to control various logic devices. The last delay element is coupled to send an active signal INTERLOCK to the event detector.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.